Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.
When using inter-chip high-speed signaling, noise and coupling between signal lines (crosstalk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its complement to a differential receiver. In this manner, noise and coupling affect both the signal and the complement equally. The differential receiver only senses the difference between the signal and its complement as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and crosstalk have on signal quality.
When high speed data is transmitted between chips, the signal lines are characterized by their transmission line parameters. High speed signals are subject to reflections if the transmission lines are not terminated in an impedance that matches the transmission line characteristic impedance. Reflections may propagate back and forth between driver and receiver and reduce the margins when detecting signals at the receiver. Some form of termination is therefore usually required for all high-speed signals to control overshoot, undershoot, and increase signal quality. For differential signaling, parallel transmission lines are used. Each transmission line may be terminated with respect to their individual characteristic impedance or the differential pair may be terminated with a resistance between the two transmission lines equal to the differential line impedance.
As the frequency of the data and clock signals increase, the amount of skew between the data signals and the clock signal in a clock group becomes important. The delay of the transmission path may be several clock cycles. To accurately detect data and to align all of the data signals before sending to core logic in a receiving chip, the data signals are delayed relative to the clock until an optimum sampling time is achieved. This is ideally in the middle of the eye window of the data signals. Since the data signals are sampled with a clock, the amount of delay in the delay line in the data paths is relative to the clock signal. If environmental factors cause the delay of the delay line to vary, then accurately sampling the clock may be compromised or may cause errors.
Signal quality may be increased by compensating for high frequency losses. It is well known that any repetitive signal or pattern may be decomposed in to its various Fourier frequency components. Such a decomposition of a generated signal and a signal received over a transmission line would show that high frequency content is attenuated more than lower frequency content. To compensate for these effects, one may decrease the low frequency content, boost the high frequency content or do both. Frequency compensation may be incorporated at the source or driver side, within the transmission network, at the receiver side, or both. Simply boosting the high frequency content above a non compensated level may also increase the high frequency noise.
There is, therefore, a need for circuitry implementing driver side controllable high frequency compensation for use with a differential receiver to improve the data eye pattern on the receiver side using a standard or a frequency compensated differential receiver.